EDN

SystemVerilog assertions unify design and verification

The SystemVerilog standard is the result of an industry-wide effort to extend the Verilog language in a consistent way to include enhanced modeling and verification features. By adding verification ...
EDN

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...
Semiconductor Engineering

Working With Custom Checkers In Dynamic Simulation Of Low Power Designs

Power-aware simulators can provide a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA ...
Electronic Design

EDA> Design And Verification Evolves With SystemVerilog

SystemVerilog is the natural evolution of the Verilog language, extending its capabilities for both design and verification. Demand for this advanced language is clear. Over a dozen EDA companies ...
Design-Reuse

Synopsys Donates Library of Advanced SystemVerilog Assertion Checkers to Accellera Standards Organization

MOUNTAIN VIEW, Calif., July 26, 2006--Synopsys, Inc. (Nasdaq:SNPS), a world leader in semiconductor design software, today announced that it has donated a library of advanced SystemVerilog assertion ...
Semiconductor Engineering

The Assertion Conundrum

It is well documented and widely agreed that assertions can provide a tremendous benefit to design and verification teams by reducing and even eliminating debug – but their use is still not ubiquitous ...
Design-Reuse

Advanced Techniques for IP Design and Verification

As designs grow in size and complexity, the challenges associated with low power and the growing design and verification gap have created the need for a paradigm shift in the IP design and ...