Forbes

SiFive Is Leading The Way For Innovation On RISC-V

The company appears well positioned to challenge CPU incumbents with high performance RISC-V CPUs and Vector Extensions to the open ISA architecture. The RISC-V CPU Instruction Set Architecture (ISA) ...
Semiconductor Engineering

Smarter Write Barriers For Arm64 In .NET CoreCLR

Introducing multiple Arm64 variants of the JIT_WriteBarrier function. Each variant is tuned for a GC mode. Because many parts ...
Business Wire

SiFive Enhances Popular X280 Processor IP to Meet Accelerated Demand for Vector Processing

SAN MATEO, Calif.--(BUSINESS WIRE)--SiFive Inc., the founder and leader of RISC-V computing, today announced the release of the latest version of its SiFive® Intelligence™ X280 processor, which ...
Electronic Design

Scalable Vector Extensions Expand the ARMv8-A's Scope

ARM’s Scalable Vector Extensions for the ARMv8-A architecture expands its scope to supercomputing and high performance embedded systems. ARMâ s Scalable Vector Extensions (SVE) for the ARMv8-A builds ...
Design-Reuse

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications

The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized ...
Semiconductor Engineering

A Sneak Peek Into SVE And VLA Programming

Download this white paper to get an overview of SVE, get information on the new registers and the new instructions, and learn about the Vector Length Agnostic (VLA) programming technique, including ...