As AI chips get larger, it becomes much harder to test them. Today, there can be as many as 22,000 pins on a 150mm² die, but in the future that number may increase to 80,000 pins. That creates a huge ...

Along with showing excellent electrical conductivity, the printed fabrics continued to perform well after 20 cycles of ...

AI export rule to be scrapped; SEMI, EU request; Cadence, Nvidia supercomputer; AI co-processor; Imagination's new GPU; semi sales up; imec, TNO photonics lab; NSF key to national security; flexible ...

Circuits are being pushed harder and longer, particularly with AI, speeding up the aging of data paths. Photonics adds its ...

Exploiting CPU Cache Side-Channels to Leak Tokens from Large Language Models” was published by researchers at MITRE and Worcester Polytechnic Institute. Abstract “Side-channel attacks on shared ...

A new technical paper titled “Coherent EUV scatterometry of 2D periodic structure profiles with mathematically optimal ...

A new technical paper titled “Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors” was ...

Newly proposed U.S. legislation called the Chip Security Act would use location verification tracking as a tool to help combat chip smuggling. This follows a report by the Economist that showed Taiwan ...

Special report on die-to-die interconnect standards; chiplet development flows; AI accelerators move out from data centers; optimizing analog; UALink; power intent; HBM4.

Chiplets will be a key enabler for customizing designs at every level, from edge devices to the cloud. AI is a key driver, ...

They depend on careful coordination between RTL, verification and implementation teams. And here’s where things get tricky. Without a consis­tent way to describe and validate power intent across the ...