Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their SoCs targeting mobile, automotive, and ...

Single Port Register File compiler - TSMC 90 nm uLL - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 40 kbits View Single Port Register File compiler - Memory ...

The ODT-ADP-14B300M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaking low power SWIFT technology. This 14-bit ADC ...

The SM-CTDSM-800M is a 12-bit continuous-time delta-sigma (CTΔΣ) analog-to-digital converter IP. By leveraging Seamless’ patented Switched-Mode Signal Processing (SMSP) technology, our ADC seamlessly ...

The IP is a 16-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC). It comprises of a second-order discrete-time modulator followed by a third-order CIC decimation filter with programmable output ...

Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Express (PCIe) and Serial RapidIO (SRIO) systems.

AFE24B19KS180NM is low-power, low noise 8-channel fully differential or 16 pseudo differential inputs, 24-bit, (ΔΣ) analog-to-digital converters (ADCs) with an integrated low-drift internal reference ...

Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The IP also enables latency-optimized NoC-to-NoC ...

Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI, and networking applications. The PHY’s flexible ...

The Synopsys IP Prototyping Kits, part of the IP Accelerated initiative, center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary system-on ...

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